1. Field of the Invention
This invention relates to high density multi-chip interconnect substrates, and more particularly to the formation and resulting structure of vias between conductive planes of such substrates.
2. Description of the Related Art
The increasing sophistication of microelectronics technology has spurred the development of smaller, faster and denser microelectronics circuits. This has resulted in the development of high density multi-chip interconnect (HDMI) technology. An HDMI substrate is a system of multiple layers of thin film conductor patterns, separated by polyimide dielectric layers fabricated on silicon or ceramic based carrier wafers. HDMI substrates are required to accommodate the large number of signal input/outputs on advanced integrated circuits. The substrate interconnections must be short and have well controlled electrical characteristics to propagate high speed signals with minimal delay, distortion and cross-talk. Internal layer-to-layer connections in multilayered HDMI substrates are made by means of "vias", which extend through intermediate dielectric layers to connect conductive layers on either side of the dielectric.
The two processes currently used to form vias in HDMI substrates are a plating process which forms the vias by plating metal into vias through holes opened in a photoresist plating mask, and an etching process in which vias are formed by etching holes in the dielectric layer and sputtering metal interconnects over and into the vias.
The vias will ideally have certain characteristics to optimize their performance. First, the metal deposited on the via walls should be of generally uniform thickness with no thinned or vacant areas, to assure a low impedance connection over wide temperature ranges. Second, it would be desirable to be able to fabricate vertically stacked vias. In multi-layered HDMI substrates, the electrical path from the top integrated circuit bond pad layer to the signal or power and ground planes is through a series of vias. An ability to stack the multiple vias in vertical alignment with each other minimizes the "real estate" occupied by the vias, and enables a denser packaging of IC components.
Unfortunately, neither of the prior approaches satisfies both of these conditions. Plated type pillar fabrication, in which a vertical pillar is formed as the via, is compatible with vertically stacked multiple vias because the additive plating process results in cylindrical via pillars that can be made continuous from layer to layer. Plating, however, has other disadvantages, particularly when used in conjunction with polyimide. The adherence of the polyimide to the metal plating can be compromised, since plating is a wet process and polyimide is inherently hygroscopic. For this reason, dry processing is preferable. With plated pillars it is difficult to control the pillar height and the uniformity of the plating. In addition, it is necessary to planarize the structure by etching back or mechanically lapping the dielectric to expose the tops of the vias, so that the next metal layer can make contact.
The etched via process uses a silicon dioxide or other hard, non-erodible etch mask to establish the location of the via. This results in a via profile that is significantly more vertical than horizontal. It is difficult to sputter a conductive coating onto the inner walls of such vias, and the metal can be severely thinned and even completely open in spots, making the vias defective or at least suspect in terms of their reliability and survivability over wide temperature ranges.
Another disadvantage of the etched process is an inability to form vertically stacked vias of more than two layers. Passing electrical signals from one conductive plane to another has typically been accomplished by offsetting or stair-stepping the vias; a via through one polyimide layer terminates on the metal of the underlying conductive layer, which provides a contact to another via which is laterally offset from the first one. The result is a requirement for additional circuit routing area to accommodate the staggered vias. This limitation becomes more severe as the number of routing layers and corresponding staggered vias increases.